The invention relates to a microprocessor for processing input/output data, comprising a number of first registers which operands which
store operands, PA1 are addressable via addresses at first bit positions in instruction words, and PA1 can be connected to data paths within the processor, in order to exchange the operands with at least one ALU or, via an interface, with notably external data paths.
Microprocessors of this kind are generally known and can be subdivided essentially into two categories on the basis of their construction which manifests itself notably in respect of the structure and magnitude of the various instruction words; microprocessors with a large and complex set of instructions and microprocessors with a reduced set of instructions. The latter category includes the group of so-called SPARC or RISC processors which require only a very short execution time for the majority of the individual instructions. This is based inter alia on the fact that for a given category of instructions the processing of operands takes place only from registers of a general set of registers which are addressed via addresses in the instruction word, so that the operands are immediately available, i.e. within one clock cycle.
The processing of input data and output data for peripheral apparatus poses a given problem in such processors. Such input/output data is often directly written into or read from the main memory of the processor by a special control device, or use is made of separate input/output registers which can exchange data in the processor, via a general data bus, with, for example the main memory or other registers. When a data word of a peripheral apparatus is to be processed in the internal ALU it must first be transferred to a register of the general set of registers, so that time is lost. This has a significant effect notably when a large number of input/output data is to be processed.
A signal processor is known (PD .mu. PD 7720 from NEC) in which one instruction can address two registers, at least one of which may be a direct input/output register for direct data exchange with peripheral apparatus. However, such a register cannot be used for general purposes. Thus, an address is dedicated to an input/output register and hence is, not available for a general purpose register. Consequently, the number of general purpose registers that can be used for a given address length is reduced.